Website Google
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- 4 years of relevant work experience.
- Experience verifying designs (CPUs, accelerator/peripheral IPs) and with verification methodologies.
- Experience with SystemVerilog, SVA, and functional coverage.
Preferred qualifications:
- Master’s degree in Electrical Engineering.
- Experience in a procedural programming language (e.g., C++, Python, Go).
- Experienced in the full verification lifecycle.
- Experience with industry-standard simulators, revision control systems, and regression systems.
About the job
As a member of an extraordinarily creative, motivated and talented team, you develop new products. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.
You’ll work closely with ASIC Design and Software Engineers to verify complex digital design systems. You will apply your UVM, SystemVerilog coding and problem-solving skills on multiple active projects. You will be responsible for full verification life-cycle, including planning, building new test environments, enhancing verification methodology, debug and coverage closure.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Responsibilities
- Plan the verification of complex digital design blocks by fully understanding design specifications. Interact with Design Engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog/UVM. Verify designs with SVA and formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with Design Engineers to deliver functionally correct design blocks and close coverage measures to identify verification holes and show progress towards tape-out. Debug, run, and measure performance on end-to-end workloads.
- Work closely with SDK, system, and software teams to ensure integration with Google’s software stack.